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NTD3055-094 Power MOSFET 12 Amps, 60 Volts
N-Channel DPAK
Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits.
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Lower RDS(on) Lower VDS(on) Lower and Tighter VSD Lower Diode Reverse Recovery Time Lower Reverse Recovery Stored Charge Power Supplies Converters Power Motor Controls Bridge Circuits
12 AMPERES 60 VOLTS RDS(on) = 94 m
N-Channel D
Typical Applications
G 4 4 Value 60 60 "20 "30 12 10 45 48 0.32 2.1 1.5 -55 to +175 61 Adc Apk W W/C W W C mJ 4 Drain YWW NTD 3055-094 RJC RJA RJA TL 3.13 71.4 100 260 C/W 1 Gate 2 Drain 3 Source 1 Gate 2 Drain Unit Vdc Vdc Vdc VGS VGS ID ID IDM PD 12 3 CASE 369A DPAK (Bent Lead) STYLE 2 NTD3055-094 Y WW 1 2 3 S
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 10 M) Gate-to-Source Voltage - Continuous - Non-Repetitive (tpv10 ms) Drain Current - Continuous @ TA = 25C - Continuous @ TA = 100C - Single Pulse (tpv10 s) Total Power Dissipation @ TA = 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1) Total Power Dissipation @ TA = 25C (Note 2) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, L = 1.0 mH IL(pk) = 11 A, VDS = 60 Vdc) Thermal Resistance - Junction-to-Case - Junction-to-Ambient (Note 1) - Junction-to-Ambient (Note 2) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR
CASE 369 DPAK (Straight Lead) STYLE 2 = Device Code = Year = Work Week
MARKING DIAGRAMS & PIN ASSIGNMENTS
4 Drain YWW NTD 3055-094
TJ, Tstg EAS
3 Source
C
1. When surface mounted to an FR4 board using 1 pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2).
ORDERING INFORMATION
Device NTD3055-094 Package DPAK Shipping 75 Units/Rail 75 Units/Rail 2500/Tape & Reel
DPAK NTD3055-094-1 Straight Lead NTD3055-094T4 DPAK
(c) Semiconductor Components Industries, LLC, 2001
1
September, 2001 - Rev. 2
Publication Order Number: NTD3055-094/D
NTD3055-094
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (Note 3) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (Note 3) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static Drain-to-Source On-Resistance (Note 3) (VGS = 10 Vdc, ID = 6.0 Adc) Static Drain-to-Source On-Voltage (Note 3) (VGS = 10 Vdc, ID = 12 Adc) (VGS = 10 Vdc, ID = 6.0 Adc, TJ = 150C) Forward Transconductance (Note 3) (VDS = 7.0 Vdc, ID = 6.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 12 Adc, Vd Ad VGS = 10 Vdc) (Note 3) SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage Reverse Recovery Time (IS = 12 Adc, VGS = 0 Vdc, Ad Vd dIS/dt = 100 A/s) (Note 3) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperatures. (IS = 12 Adc, VGS = 0 Vdc) (Note 3) (IS = 12 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr ta tb QRR - - - - - - 0.94 0.82 33.1 24 8.9 0.047 1.15 - - - - - C Vdc ns (VDD = 48 Vdc, ID = 12 Adc, VGS = 10 Vdc, RG = 9.1 ) (Note 3) td(on) tr td(off) tf QT Q1 Q2 - - - - - - - 7.7 32.3 25.2 23.9 10.9 3.1 4.2 15 70 50 50 20 - - nC ns (VDS = 25 Vdc, VGS = 0 Vdc, Vd Vd f = 1.0 MHz) Ciss Coss Crss - - - 323 107 34 450 150 70 pF VGS(th) 2.0 - RDS(on) - VDS(on) - - gFS - 0.85 0.77 6.7 1.35 - - mhos 84 94 Vdc 2.9 6.3 4.0 - Vdc mV/C mOhm V(BR)DSS 60 - IDSS - - IGSS - - - - 1.0 10 100 nAdc 68 54.4 - - Vdc mV/C Adc Symbol Min Typ Max Unit
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NTD3055-094
24 VGS = 10 V ID, DRAIN CURRENT (AMPS) 20 16 12 5.5 V 8 5V 4 0 4.5 V 0 1 2 3 4 5 9V 8V 6V 7V ID, DRAIN CURRENT (AMPS) 6.5 V 20 16 12 8 TJ = 25C 4 0 3 3.5 4 4.5 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ = 100C 24 VDS 10 V
TJ = -55C 5 5.5 6 6.5 7 7.5 8
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
RDS(on), DRAIN-TO-SOURCE RESISTANCE () RDS(on), DRAIN-TO-SOURCE RESISTANCE ()
Figure 2. Transfer Characteristics
0.20 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 0 4 8 12 16 20 24 ID, DRAIN CURRENT (AMPS) TJ = 25C TJ = -55C VGS = 10 V TJ = 100C
0.20 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 0 4 8 12 16 20 24 ID, DRAIN CURRENT (AMPS) TJ = -55C TJ = 25C TJ = 100C VGS = 15 V
Figure 3. On-Resistance versus Gate-to-Source Voltage
RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 2 1.8 1.6 1.4 1.2 1 0.8 0.6 -50 -25 1 0 25 50 75 100 125 150 175 0 ID = 6 A VGS = 10 V IDSS, LEAKAGE (nA) 100 1000
Figure 4. On-Resistance versus Drain Current and Gate Voltage
VGS = 0 V
TJ = 150C
10
TJ = 100C
10
20
30
40
50
60
TJ, JUNCTION TEMPERATURE (C)
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-to-Source Leakage Current versus Voltage
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NTD3055-094
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
800 VDS = 0 V Ciss C, CAPACITANCE (pF) 600 VGS = 0 V TJ = 25C
400
Crss Ciss
200 Coss 0 10 5 VGS 0 VDS 5 Crss 10 15 20 25
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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NTD3055-094
VGS , GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 8 Q1 6 4 2 0 0 2 4 6 8 10 QG, TOTAL GATE CHARGE (nC) 12 ID = 12 A TJ = 25C 1 1 10 RG, GATE RESISTANCE (OHMS) 100 VDS = 30 V ID = 12 A VGS = 10 V Q2 QT VGS t, TIME (ns) tr td(off) tf td(on) 100
10
Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS
16 IS, SOURCE CURRENT (AMPS) 14 12 10 8 6 4 2 0 0.6 0.68 0.76 0.84 0.92 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) 1 VGS = 0 V TJ = 25C
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
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NTD3055-094
SAFE OPERATING AREA
EAS , SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 100 I D, DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C 10 100 s 1 ms 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 10 1 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 100 dc 10 s 70 ID = 11 A 60 50 40 30 20 10 0 25 175 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (C)
1
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)
Figure 11. Maximum Rated Forward Biased Safe Operating Area
Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature
1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 0.00001 0.0001 0.001 0.01 t, TIME (s) 0.1 1 10 t2 DUTY CYCLE, D = t1/t2 t1 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)
Figure 13. Thermal Response
di/dt IS trr ta tb TIME tp IS 0.25 IS
Figure 14. Diode Reverse Recovery Waveform
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NTD3055-094
PACKAGE DIMENSIONS
DPAK CASE 369A-13 ISSUE AA
SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. DIM A B C D E F G H J K L R S U V Z INCHES MIN MAX 0.235 0.250 0.250 0.265 0.086 0.094 0.027 0.035 0.033 0.040 0.037 0.047 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.175 0.215 0.020 0.050 0.020 --0.030 0.050 0.138 --MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.84 1.01 0.94 1.19 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.45 5.46 0.51 1.27 0.51 --0.77 1.27 3.51 ---
-T- B V R
4
C E
A S
1 2 3
Z U
K F L D G
2 PL
J H 0.13 (0.005)
M
T
STYLE 2: PIN 1. 2. 3. 4.
GATE DRAIN SOURCE DRAIN
DPAK CASE 369-07 ISSUE M
B V R
4
C E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. DIM A B C D E F G H J K R S V INCHES MIN MAX 0.235 0.250 0.250 0.265 0.086 0.094 0.027 0.035 0.033 0.040 0.037 0.047 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.175 0.215 0.050 0.090 0.030 0.050 MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.84 1.01 0.94 1.19 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.46 1.27 2.28 0.77 1.27
A
1 2 3
S -T-
SEATING PLANE
K
F D G
3 PL M
J H 0.13 (0.005) T
STYLE 2: PIN 1. 2. 3. 4.
GATE DRAIN SOURCE DRAIN
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NTD3055-094
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PUBLICATION ORDERING INFORMATION
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NTD3055-094/D

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